The present invention pertains to on-chip test circuitry. More particularly, the present invention pertains to a logical built-in self test (LBIST) circuit for selectively testing channels in a microprocessor or other complex semiconductor circuitry.
There are numerous on-chip test circuitry schemes available in the art. For example, the IEEE 1149.1 (Joint Test Action Group (JTAG) 1990), provides an on-chip testing system that includes a scan chain. The scan chain includes a plurality of elements, where each element includes a flip-flop or latch. During initialization, a first set of input data is provided to the first flip-flop of each of the test channels. A scan clock is used to move this data from the first flip-flop into the test channel. At the same time, the next set of input data is provided to the first flip-flops. Each scan chain element is coupled to a subset of logic on the chip to be tested (i.e., the test channel). The initialization procedure continues until the desired data for each scan chain element is loaded into the corresponding flip-flops. A functional clock can then be used to operate the logic to be tested to utilize the data. The output data for the logic is provided to the next flip flop so that it can be moved on to one or more successive flip-flops until it reaches off chip drivers or the like for analysis. Thus, based on known input data, the logic to be tested will take this data and provide expected output data. If there is a difference between the actual output data and the expected output data, then there is an error in the tested logic.
In a JTAG system, the chip is typically coupled to a testing system. Via the testing system, certain registers on the chip may be loaded with desired values and/or read. Data tends to be input through a test access port (TAP) for the chip. There are several problems, however, with the JTAG systems that are present in the art. First, test data generation and diagnostics are done off-chip, which can lead to limited test coverage due to test data volume and/or excessive test time. Second, performing LBIST testing consumes a vast amount of power, in part because of the large number of clocking signals that are generated and because of the large number of electrical nodes that toggle simultaneously during LBIST. Third, result data from the LBIST scan channels often results in a lot of data which is unnecessary or not needed.
In view of the problems set forth above, there is a need for an on-chip testing architecture that improves the tester's ability to generate test data, diagnose problems, conserve power, and filter or mask results.